The present invention relates generally to coating, and more particularly to coating wherein a semiconductor product is produced.
Chemical Vapor Deposition (hereafter CVD) is one of the preferred techniques to prepare large area semiconductor devices. As the name implies, the technique involves the deposition from the gas phase of elements or compounds over a suitable "substrate." Ideally a perfect crystallographic lattice match between the deposited material and the substrate is preferred, and the coefficients of expansion of the substrate and the deposited material should be the same or very close. When these conditions are met, it is possible to obtain smooth deposited layers on the substrates and to change the temperature of the systems without the limitations introduced by differential expansion. If on the other hand, the thermal expansions of substrates and deposited layers are different, severe complications arise. In particular, the stresses due to temperature changes can result in breaking, cracking, bending and peeling off of the deposited layers (which are usually much thinner than the substrates). For these reasons, and, additionally, because of purity requirements, the preferred substrate for the CVD of silicon is a silicon wafer, the preferred substrate for the CVD of gallium arsenide is a GaAs wafer, and so on. If a large area substrate of the material whose CVD is wanted does not exist, one looks for other suitable substrates. In the case of silicon carbide, SiC, large area wafers of SiC are not available, because SiC dissociates before melting and it is impossible to prepare "boules" of single-crystal SiC to be sliced and polished. Crystals with similar structure and compatible lattice dimensions, e.g., aluminum nitride, AlN; boron phosphide, BP; etc., are not commercially available. However, they could introduce electrically active impurities in the layers of deposited SiC. For these and other reasons, a preferred substrate for the CVD of SiC is silicon, which is easily available and is not an impurity in SiC. Unfortunately, silicon is a very poor match to SiC, both from the standpoint of lattice dimensions and thermal expansion. Thus, the lattice dimension (cubic cell edge) of SiC is 4.359 angstroms at room temperature, while the lattice dimension of Si is 5.430 angstroms. Also large differences in the thermal expansions exist, which depend on the temperature interval considered.
It follows that while the process of CVD of SiC on Si may be performed without difficulties, the recovery of the deposited layers may be prevented by cracking and breaking of the layers when the temperature is changed from deposition temperature down to room temperature. Experience has shown that good quality crystalline layers of SiC are preferentially obtained at high temperatures. Using silicon as substrate, this means that one can operate up to the melting point of silicon, which is close to 1410.degree. C. Taking 1400.degree. C. as a practical upper limit for the CVD of SiC on Si, when the deposition process is terminated, one is left with the problem of how to bring the grown layers intact from approximately 1400.degree. C. down to room temperature. It is found that only extremely thin layers of SiC on Si, a few hundred angstroms at the most, can survive the cooling process without introduction of stresses, mechanical defects or breakage. These limitations are obvious from the literature on CVD of SiC on Si, in particular the following references: D. M. Jackson and R. W. Howard, Trans. Metall. Soc. AIME 223, 468 (1965); H. Matsunami, S. Nishino and T. Tanaka, J. of Crystal Growth 45, 138 (1978); S. Nishino, Y. Hazuki, H. Matsunami and T. Tanaka, J. Electrochem. Soc. 127; 2674 (1980); W. G. Spitzer et al., Intern. Conf. on Silicon Carbide, Boston, Mass. 1959 pp. 347-364.